Structured ASICs, also referred to as platform ASICs, may be used as target devices to implement systems. The pre-defined metal layers of structured ASICs helps reduce manufacturing cycle time when compared to using full custom ASICs. Pre-characterization of what is on silicon also helps reduce design cycle time may be reduced when compared to using full custom ASICs.
In a structured ASIC design, logic mask-layers of a device are pre-defined by the ASIC vendor. Design differentiation and customization are achieved by creating custom metal layers that create custom connections between predefined lower-layer logic elements. Structured ASIC technology bridges the gap between field programmable gate arrays (FPGAs) and full custom ASIC designs. Since a smaller number of chip layers must be custom produced compared to a full custom ASIC design, structured ASIC designs have smaller non-recurring expenditures than full custom ASIC or full custom chips which require a full mask set be produced for every design.
Structured cells constructed from a collection of logic transistors on a structured ASIC may be used to construct logic for the system. The structured cells allow flexible functionality such that a single structured cell or a combination of structured cells may be used to implement any logic required. Only the structured cells needed to implement the system are assembled together, which optimizes the structured cell use. Unused areas of a structured cell logic fabric may be powered down, resulting in power savings.
In the past, when structured ASIC designers designed the architecture of the structured cells, functions from existing system designs were transformed to binary decision diagrams and implemented by the primary components of simple structured cells for evaluation. This approach, however, approximated the capacity of the structured cell with the primary components of the structured cell and underutilized the capability of the other components of the structured cell.